1. Field of the Invention
The present invention is related to a Conductive Bridge Random Access Memory (CBRAM) memory device having a plurality of resistive memory cells. The invention is further related to a method for writing to resistive memory cells in a CBRAM memory device.
2. Description of the Related Art
A CBRAM memory device (also called a PMC memory device, PMC: Programmable metallization cell, and a PCRAM memory device, PC: programmable conductor) includes a plurality of resistive memory cells. The resistive memory cells each comprise a resistive memory element and, optionally, depending on the design of the CBRAM memory device a selection transistor for addressing the respective resistive memory cell. The resistive memory element formed by a PMC element, for instance, comprise a solid state electrolyte (e.g. a chalcogenide material) in which an electrically conductive path can be established or degenerated depending on the electrical field applied thereon. Thereby, different resistance states can be acquired in the resistive memory element which can be utilized to store an information.
In a resistive memory element in which two different resistance states can be set a first low resistance state can be acquired by applying a voltage (electrical field) which is higher than a programming threshold voltage and a high resistance state can be acquired by applying a voltage (electrical field) which is lower than an erasing threshold voltage. Usually the programming threshold voltage and the erasing threshold voltage are reverse in sign.
Provided that the CBRAM memory device is supplied by an externally provided operating voltage two main concepts for writing into a resistive memory cell are known. In one concept, in a CBRAM memory device the resistive memory element is coupled with a common electrode which is usually called plate element and a further terminal of the resistive memory element is coupled or can be coupled with a bit line. Usually the plate electrode is hold on a constant reference potential which is set as a potential which is in the middle between a high operating potential and a low operating potential supplied to the CBRAM memory device as the operating voltage. A positive electrical field can be applied on the resistive memory element by connecting the bit line with the high operating potential, and a negative electrical field can be applied by connecting the bit line with the low operating potential or vice versa depending on the polarity of the resistive memory element. Thereby, the programming or erasing voltage for changing the resistance state of the resistive memory element is then about the half of the operating voltage.
In a further concept the plate potential is not set to constant potential but to one of the high and the low operating potential and the further terminal of the resistive memory element to the low and high operating potential, respectively depending on the resistance state which is to be written to the resistive memory element. In this concept, the maximum voltage for programming and for erasing equals the operating voltage.
The time for changing the resistance state of a resistive memory element depends substantially on the applied programming and erasing voltage, respectively. Thus, the minimum time which is needed for re-writing the resistive memory element is predetermined.